Nu blin, ugovorila
Alexei D******
******, Rochester, MN 55901
(858) 344-3262
[email protected]
EDUCATION:
Drexel University, Philadelphia, PA
Bachelor of Science in Electrical & Computer Engineering, Graduated in June 2000
QUALIFICATIONS:
Digital Design Engineer with experience in ASIC/SoC development using Verilog and VHDL including block and system level verification, PCB/PWB design, design entry, simulation, low level programming and excellent laboratory skills.
PROJECTS:
**** ASIC : MARCH 2004 - PRESENT
System Level Verification Engineer
- Bringup testcase generation
- Directed manual testcase generation
- Random test regressions
- Hardware and simulation environemnt problem identification and resolution
Copernicus ASIC : MAY 2001 - JULY 2002
Ethernet MAC Manager Transmit Chain Block Owner
- Open Core Protocol (OCP) Bus Implementation
- RTL code using Verilog hardware definition language
- Behavioral Testbenches
- Physical synthesis
- Timing closure
- Formal verification
- Signal integrity analysis
- Power analysis
Hamming ASIC : MARCH 2001 - APRIL 2001
ASIC Emulator Board Test Environment Designer
- Devised a CLI design environment using C programming language
- Low level programming for a PIC processor
Everest ASIC : OCTOBER 2000 - FEBRUARY 2001
System Level Verification Tester for Link List Memory Controller Block
- High level behavioral testbenches
- Test instructions for a MIPS core using C programming language
- Test instructions for a sequencer core using Assembly programming language
Pipeline ASIC : AUGUST 2000 - SEPTEMBER 2000
Design Verification Tester
- Laboratory testing of an ASIC emulator board
- Design Verification Testing report
Drexel University Six Legged Electronic Robot (DUSLER)
Senior Design Project : SEPTEMBER 1999 - MAY 2000
Project Group Member - PCB Designer
- Upgrade for obsolete robot control systems
- Definition of technical guidelines and schedule
- PCB Design and verification
- Laboratory testing
- Project documentation and presentation
Crossbow Advanced Cable Head-End : SEPTEMBER 1998 - MARCH 1999
Laboratory Tester/Technician - CAD Engineer
- Procurement of electronic components for engineering PCB prototypes
- Building of prototypes
- Laboratory testing
- Schematic entry using Cadence Concept
SKILLS:
CAD/CAE:
- Verilog
- VHDL
- Verilint
- Verisure
- Synopsis
- Signalscan
- Innoveda
- VisualELITE
- Cadence Concept
- AutoCAD
- LabVIEW
- OrCAD
- Pspice
- Matlab
- S3
COMPUTER:
HARDWARE:
- IBM PC
- MAC
- SUN
- HP
SOFTWARE:
- Windows
- Mac OS
- Unix/Linux
- MS Office
PROGRAMMING:
- C
- Assembly
LABORATORY EQUIPMENT:
- Oscilloscope
- Network Analyzer
- Logic Analyzer
- Multimeter
- Power Supply
- Soldering Iron
- Desoldering Equipement
EXPERIENCE:
IBM, Rochester, MN
ASIC Verification Engineer - Consultant : MARCH 2004 - PRESENT
System level verification of an SoC - Design of testcases - Random testcase regressions - Coverage generation
Hughes Network Systems, San Diego, CA
Member of Technical Staff II : APRIL 2002 - AUGUST 2002
Member of Technical Staff I : AUGUST 2000 - MARCH 2002
ASIC Engineer - Complete owner of entire physical design flow for an ASIC block including RTL-coding, testbenches, timing closure and power analysis - Test environment design for an ASIC emulation board - System level verification on an ASIC - Design verification testing of an ASIC emulator board.
General Instrument Corporation (Currently Motorola Broad Band Division), Horsham, PA
Electrical Engineering Co-op Student : SEPTEMBER 1997 - MARCH 1998
Electrical Engineering Co-op Student : SEPTEMBER 1998 - MARCH 1999
PCB/PWB Design entry - Circuit prototype builds - Board level verification for an advanced cable head-end product - Analog circuit modeling.
Roberts Water Technologies, Inc, Darby, PA
Project Engineer-s Assistant/Co-op student : SEPTEMBER 1996 - MARCH 1997
Electrical and mechanical design entry - PC technical support - Resolving computer related issues and expanding/upgrading the company network - Filter plant start up assistance - Tests and experiments related to water filtration plant design.
OTHER:
Drexel University, Philadelphia, PA
Mentoring inner city middle school students
as part of a Saturday extracurricular advancement program : SEPTEMBER 1996 - JUNE 1997
Tutoring students in Calculus Mathematics and Physics JANUARY : 1996 - JUNE 1996
UCSD, San Diego, CA
Graduate computer and electrical engineering coursework : SEPTEMBER 2000 - DECEMBER 2000
VLSI Engineering and Advanced Communications classes
PennState University, Ogonz, PA
Undergraduate engineering coursework while in High School : SEPTEMBER 1994 - JUNE 1995
Classes in AutoCAD, Drafting and Engineering Ethics
HONORS & AFFILIATIONS:
Dean-s List : FALL 1995 & SPRING 1997
Member of IEEE and PSPE : 2000
REFERENCES: Available Upon Request
